---------------------------------------------------------------------------
-- Company     : EIA / HTA 
-- Author      : Yves Peissard <ypeissard@gmail.com>
-- 
-- Creation Date : 23/04/2009
-- File          : modeSwitcher.vhdl
--
-- Abstract : This is the testbench file for the modeSwitcher block
--            of the iTimer project.
--            The busMode is initiated to "00" (editMode).
--
--            busMode = "00" => Edit mode
--			  busMode = "01" => Timer
--		      busMode = "10" => Pause
--		 	  busMode = "11" => Alarm
-- 
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity modeswitcher_tb is
end modeswitcher_tb;

architecture testbench1 of modeswitcher_tb is

  -- component decleration
  component modeSwitcher is
	port(
		busMode                              : out std_logic_vector(1 downto 0); 
		alarm,simplePush,longPush,clockInput : in  std_logic
	);
  end component modeSwitcher;

  -- internal signals
  signal busMode: std_logic_vector (1 downto 0) := "00";
  signal alarm,simplePush,longPush : std_logic := '0';
  signal clockInput : std_logic := '0';

  -- constants
  constant period : time := 50 ns; -- used to generate the clock signal

  
  begin --architecture
  -- instantiation of modeSwitcher component
  mS: modeSwitcher 
  port map(
	  busMode=>busMode,
	  alarm=>alarm,
	  simplePush=>simplePush,
	  longPush=>longPush,
	  clockInput=>clockInput);
   

  -- process which generates a clock signal
  generate_clock : process (clockInput)
  begin -- process
     clockInput <= NOT clockInput after period/2;
  end process;

  -- main process of the testbench
  process 
  begin
       wait for 2*period + 66 ns;

	   simplePush <= '1'; -- go to timer mode
       wait for period;
	     assert (busMode = "01") report "busmode should be 01 here";
	   simplePush <= '0'; 
	   wait for period;

	   simplePush <= '1'; -- go to pause mode
       wait for period;
	 	  assert (busMode = "10") report "busmode should be 10 here";
	   simplePush <= '0';
       wait for period;

	   simplePush <= '1'; -- go to timer mode
       wait for period;
	 	  assert (busMode = "01") report "busmode should be 01 here";
	   simplePush <= '0';
       wait for period;

	   longPush <= '1'; -- go to edit mode
       wait for period;
	 	  assert (busMode = "00") report "busmode should be 00 here";
	   longPush <= '0';
       wait for period;

	   simplePush <= '1'; -- go to timer mode
       wait for period;
	 	  assert (busMode = "01") report "busmode should be 01 here";
	   simplePush <= '0'; 
	   wait for period;

	   alarm <= '1';      -- set alarm
       wait for 2*period;
	 	  assert (busMode = "11") report "busmode should be 11 here";
	    
	   simplePush <= '1'; -- go to edit mode (cancel the alarm by a simplepush)
       wait for period;
	 	  assert (busMode = "00") report "busmode should be 00 here";
	   simplePush <= '0'; 
	   alarm <= '0';
	   wait for period;

	   longPush <= '1'; -- go to timer mode
	   wait for period;
	   		assert (busMode = "01") report "busMode should be 01 here";
	   longPush <= '0';
	   wait for period;

	   simplePush <= '1'; -- go to pause mode
	   wait for period;
	   		assert (busMode = "10") report "busMode should be 10 here";
	   simplePush <= '0';
	   wait for period;

	   longPush <= '1';
	   wait for period;
	   		assert (busMode = "00") report "busMode should be 00 here";
	   longPush <= '0';
       wait for period;


        
	   assert false report "simulation finished" severity note;
       wait;
	end process;	
end architecture;
